1. Field
This disclosure relates generally to semiconductor integrated circuit devices, and more specifically, to semiconductor systems on a chip with one or more processing devices and a radio frequency transceiver.
2. Related Art
There is increasing demand for a low cost radio frequency (RF) transceiver integrated in a system-on-a-chip (SoC) with an embedded controller or processor and other peripherals for use in smart home, life, sensors, etc. in a market segment sometimes referred to as the internet of things (IOTs). A constant envelope RF transceiver is commonly used for low cost low data rate applications that includes a single phase locked loop (PLL) for both the receive and transmit operations. The PLL is a control system that generates a signal whose phase is related to the phase of an input signal.
To operate a PLL with a wide frequency range, a Voltage Controlled Oscillator (VCO) is first tuned to a frequency that approximates the radio carrier frequency desired (Coarse Tune), and the PLL is then engaged to lock the VCO frequency to a targeted channel frequency, which is a fractional multiple of a tightly controlled reference oscillator (Fine Tune). Regulations for transmission require that before any radio transmission is put on-air, especially in industrial, scientific and medical (ISM) radio frequency (RF) bands, radio radiated emissions be within the limits set by the Federal Communications Commission (FCC) for an allocated frequency channel.
Receive operation requires the PLL to remain locked at a desired channel frequency for an extended period of time. If the PLL frequency drifts, an incoming RF signal might not be received correctly, leading to degraded communication quality as well wasted power consumption. Correct transmit/receive operation requires the transceiver to confirm that the PLL has locked the VCO at the correct desired frequency.
Further there is a need to monitor the PLL on an on-going basis to ensure the frequency does not drift and violate the FCC rules.
The existing methods of monitoring the PLL on an on-going basis are slow and have a high rate of false alarms. Cycle slip detection requires a significant number of samples of the reference clock and the divided down PLL clock in order to determine Lock State. During this slow detection time, the transceiver may be significantly off target frequency wasting power and violating the FCC rules.